Code of art

Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad mini

On a Design Race

Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad mini

Ethics of Art

Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor incididunt ut labore et dolore magna aliqua. Ut enim ad mini

Key trend in Storage Industry

Doubling density – QLC will become mainstream in 2020 and capacity will goes to 1TB built-in for flagship 5G mobile phones. SSD, NVME will also equip with that

High performance – performance increase by adding cores and channels within ASIC. Chip size and power consumption increase as LDPC efficiency remains. Shrinking die size and lower power consumption is market’s key target

 

Traditional LDPC has a bottleneck in performance. Controller company will use more core and channel to achieve higher performance. But this will also increase the area of ASIC, Power, Heat and COST.
So here are 3 key things a controller or storage company needs to pay attention to be able to service the market going forward?

Key factors that determines the future of controllers in Memories and Storage market

Silicon performance

Less silicon – Less design area on SoC

ECC performance

Cost down – one core performance with Codelucida’s IP is better than most market’s multi-core controller performance

Power consumption

Power consumption – lower power consumption than multi-core controller.

Intellectual Property

The technology enabler for delivering IP and services on 3D NAND Flash and Wireless solution. With the background of our team which highly experienced in networking, storage, semiconductor as well as business knowledge. Our goal is the deliver the best solution and serve the customer to the success.

About David B. James (DJ)

Served at Intel Flash Business Unit and Qualcomm Wireless. David has developed a strong relationship to the China market. Enabled and assisted numbers of Tier-1 customers on the flash memory products as well as wireless solutions.

Vision

With the 5G network go live and the deployment of the IoT, Automaton Driving, Robotics, AI, Payment services. They all share a common destination and sources for store, retrieve and process data. We see that the cloud storage, edge computing will require the performance, density, reliability on a new high level. That’s the reason that we engage with Codelucida, the new generation of Error Corrector LDPC IP for TLC, QLC on SSD, UFS, PCIe or up coming storage requirements.

FAID™ error correction for enabling next-gen flash memories – Custom-designed LDPC IP core provides the best performance and durability for high-density flash memory particles

1. FAID™ – Key differences

Key Differences
– Highest error-correction capability: Optimized performance to achieve the highest error-correction capability under hard-decision decoding (10% – 15% RBER gain)
– No error floor: Very low error-rates (lower than UBER of 10^(−17)) achieved with no error floor (for 1KB, 2KB, and 4KB information size)
– No LLR table: Completely eliminate use of LLR tables simplifying NAND flash media management.
– Throughput and complexity

– FPGA: Throughputs > 7GB/s (by a single core) with ability to run at the max frequency of the chip (>500MHz). Lowest FPGA resource usage in the industry. Proven IP with customers.
– ASIC: Highly scalable throughputs up to 57GB/s per iteration (by a single core) with ability to run at 1GHz at 28nm (svt standard cell), and lowest area and power usage for high thorughputs.

Complexity – FPGA resource for 4KB

Extremely favorable scaling in decoder complexity as the decoder throughput requirements increase

Encoder utilizes at most 7% of logic and 15% of memory used by decoder and these percentage resource usages do not increase even for higher throughput targets

2. Patent FAID™ – Complexity

3. Patent FAID™ – Complexity

Complexity – ASIC at 28nm

Single Core achieving up to 57GB/s per iteration @ 1GHz on 28nm. The single core provides a savings of 6x in area and power compared to using multiple smaller cores.

Encoder complexity is at most 7% of the decoder complexity and stays the same regardless of the throughput, even as throughput targets increase.

Results from FPGA – Error correction performance for 3D TLC NAND
RBER gain of 10% to 15% compared to min-sum based decoders
Numbers of errors corrected measured @ FER = 〖𝟏𝟎〗^(−𝟔)
Hard-decision decoding – 300 errors per 4KB
1 bit hard + 1 bit soft decision decoding – 608 errors per 4KB

4. Patent FAID™ – Results from FPGA

5. Patent FAID™ – Results from FPGA

Results from FPGA – Error correction performance for 3D QLC NAND
RBER gain of 10% to 15% compared to min-sum based decoders
Numbers of errors corrected measured @ FER = 〖𝟏𝟎〗^(−𝟔)
Hard-decision decoding – 432 errors per 4KB
1 bit hard + 1 bit soft decision decoding – 828 errors per 4KB

Patent FAID™ – Summary of features and benefits

Flexibility: Fully flexible architecture to support wide range of information lengths (1KB, 2KB, 4KB) + metadata, and code rates (0.83 to 0.95), with ability to change code rate on the fly with fine granularity

Encoding and Decoding: Single decoding architecture that supports hard-decision decoding, 2-bit soft-decision decoding (1 bit soft) and 3-bit soft decision decoding (2 bits soft). Extremely low-complexity encoding that can support any throughput

Improved endurance and retention: Tested with data generated from NAND characterization of the latest 3D TLC and 3D QLC NAND samples

Simplified NAND management: Robust to the choice of soft reads, reduced read-entry with appropriate hard read threshold models, and no use of LLR table.